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PRODUCT SPECIFICATION
1
Z86C72/C92/L72/L92
IR MICROCONTROLLER
FEATURES
Part Z86C72 Z86C92 Z86L72 Z86L92 ROM (KB) 16 0 16 0 RAM* (Bytes) 748 748 748 748 - I/O 31 31 31 31 Voltage Range 4.5V to 5.5V 4.5V to 5.5V 2.0V to 3.9V 2.0V to 3.9V
s
1
Programmable Input Glitch Filter for Pulse Reception
Five Priority Interrupts - Three External - Two Assigned to Counter/Timers Low Voltage Detection and Standby Mode Programmable Watch-Dog/Power-On Reset Circuits Two Independent Comparators with Programmable Interrupt Polarity On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC (mask option), or External Clock Drive Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3 - All Eight Port 2 Bits at one time or Not - Pull-Ups Automatically Disabled Upon Selecting Individual Pins as Outputs Maskable Mouse/Trackball Interface on P00 Through P03 is available on the L72 version. 32 kHz Oscillator Mask Option
Note: *General-Purpose s s s
s s
Expanded Register File Control Registers Low Power Consumption - 40 mW (typical) Three Standby Modes: - STOP - HALT - Low Voltage Automatic External ROM (Z86LX2/C72 Version) Access Beyond 16K
s
s
s
s
s
Special Architecture to Automate Both Generation and Reception of Complex Pulses or Signals: - One Programmable 8-Bit Counter/Timer with Two Capture Register - One Programmable 16-Bit Counter/Timer with One Capture Register
s
s
GENERAL DESCRIPTION
The Z86LX2/CX2 family of IR (Infrared) are ROM/ROMless-based members of the Z8(R) MCU single-chip microcontroller family with 768 bytes of internal RAM. The differentiating factor between these devices is the availability of RAM, ROM and package options. The use of external memory enables these Z8 microcontrollers to be used where code flexibility is required. Offering the 5V versions (Z86CXX) and gives optimum performance in both the low and high voltage ranges. Zilog's CMOS microcontrollers DS97LVO0900 offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up resistors. The Z86LX2/CX2 product line offers easy hardware/software system expansion with cost-effective and low power consumption. The Z86LX2/CX2 architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
GENERAL DESCRIPTION (Continued)
access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z86C72/C92/L72/L92 offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery operated hand-held applications. Many applications demand powerful I/O capabilities. The Z86LX2/CX2 family fulfills this with three package options in which the L72 version provides 31 pins of dedicated input and output. These lines are grouped into four ports. Each port consists of eight lines (Port 3 has seven lines) and is configurable under software control to provide timing, status signals, parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are five basic address spaces available to support a wide range of configurations: Program Memory, Register File, Expanded Register File, Extended Data RAM and External Memory. The register file is composed of 256 bytes of RAM. It includes four I/O port registers, 16 control and status registers and the rest are General-Purpose registers. The Extended Data RAM adds 512 bytes of usable general-purpose registers. The Expanded Register FIle consists of two additional register groups (F and D). To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Z86LX2/CX2 family offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two on-board comparators to process analog signals with separate reference voltages (Figure 2).
HI16 8
LO16 8
16-Bit T16 124 8 8 SCLK Clock Divider TC16H 16 8 TC16L And/Or Logic HI8 8 Input Glitch Filter Edge Detect Circuit 8-Bit T8 8 TC8H 8 TC8L LO8 8
Timer 16
Timer 8/16
Timer 8
Figure 1. Counter/Timer Block Diagram
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Z86C72/C92/L72/L92 IR Microcontroller
P00 P01 P02 P03 Port 0 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 Register Bus
Register File 256 x 8-Bit Port 3 Internal Address Bus ROM 16K/0K x 8 Internal Data Bus Z8 Core
P31 P32 P33 P34 P35 P36 P37
1
Port 1 Expanded Register File 512 x 8-Bit Expanded Register Bus
Machine Timing & Instruction Control
XTAL /AS /DS R/W /RESET
Port 2 Counter/Timer 8 8-Bit Counter/Timer 16 16-Bit
Power
VDD VSS
Figure 2. Functional Block Diagram
Note: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
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PIN DESCRIPTION
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VDD P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS
1
40
Z86C72/C92 Z86L72/L92 DIP
20
21
/DS P24 P23 P22 P21 P20 P03 P13 P12 VSS P02 P11 P10 P01 P00 Pref1 P36 P37 P35 /RESET
Figure 3. 40-Pin DIP Pin Assignments
P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04
7
P20 P03 P13 P12 VSS VSS P02 P11 P10 P01 P00 6 1 40 39
Z86C72/C92 Z86L72/L92 PLCC
17 18
29 28
Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31
Figure 4. 44-Pin PLCC Pin Assignments
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P05 P06 P14 P15 P07 VDD VDD P16 P17 XTAL2 XTAL1
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Z86C72/C92/L72/L92 IR Microcontroller
33 P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04 34
P20 P03 P13 P12 VSS VSS P02 P11 P10 P01 P00
1
Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31
23 22
Z86C72/C92 Z86L72/L92 QFP
44 1
12 11
Figure 5. 44-Pin QFP Pin Assignments
DS97LVO0900
P05 P06 P14 P15 P07 VDD VDD P16 P17 XTAL2 XTAL1
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Z86C72/C92/L72/L92 IR Microcontroller
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PIN DESCRIPTION (Continued)
Table 1. Pin Identification 40-Pin DIP # 26 27 30 34 5 6 7 10 28 29 32 33 8 9 12 13 35 36 37 38 39 2 3 4 16 17 18 19 22 24 23 20 40 1 21 15 14 11 31 25 44-Pin PLCC 40 41 44 5 17 18 19 22 42 43 3 4 20 21 25 26 6 7 8 9 10 14 15 16 29 30 31 32 36 38 37 33 11 13 35 28 27 23,24 1,2,34 39 12 44-Pin QFP# 23 24 27 32 44 1 2 5 25 26 30 31 3 4 8 9 33 34 35 36 37 41 42 43 12 13 14 15 19 21 20 16 38 40 18 11 10 6,7 17,28,29 22 39 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P31 P32 P33 P34 P35 P36 P37 /AS /DS R//W /RESET XTAL1 XTAL2 VDD VSS Pref1 R//RL Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Output Output Output Output Output Output Output Input Input Output Description Port 0 is Nibble Programmable Port 0 can be configured as A15-A8 external program ROM/DATA Address Bus. Port 0 can be configured as a mouse/trackball input.
Port 1 is byte programmable Port 1 can be configured as multiplexed A7-A0/D7-D0 external program ROM Address/Data Bus.
Port 2 pins are individually configurable as input or output.
IRQ2/Modulator Input IRQ0 IRQ1 T8 output T16 output T8/T16 output Address Strobe Data Strobe Read/Write Reset Crystal, Oscillator Clock Crystal, Oscillator Clock Power Supply Ground Comparator 1 Reference ROM/ROMless
Input Input
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Z86C72/C92/L72/L92 IR Microcontroller
ABSOLUTE MAXIMUM RATINGS
Symbol VCC TSTG TA Description Supply Voltage (*) Storage Temp. Oper. Ambient Temp. Min -0.3 -65 Max +7.0 +150 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
1
Notes: * Voltage on all pins with respect to GND See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 6).
From Output Under T est
I
150 pF
Figure 6. Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF
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DC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary TA = 0C to +70C Sym Parameter VCC Min 7 7 0.8 VCC 0.8 VCC VSS - 0.3 VSS- 0.3 0.7 VCC 0.7 VCC VSS - 0.3 VSS - 0.3 VCC - 0.4 VCC - 0.4 VCC - 0.8 VCC - 0.8 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC 0.5VCC 0.5VCC 0.5VCC 0.5VCC 1.7 3.7 Max Max Input Voltage 2.0V 3.9V VCH Clock Input High Voltage 2.0V 3.9V VCL Clock Input Low Voltage 2.0V 3.9V VIH VIL VOH1 VOH2 Input High Voltage 2.0V 3.9V Input Low Voltage 2.0V 3.9V Output High Voltage Output High Voltage (P36, P37,P00, P01) 2.0V 3.9V 2.0V 3.9V Typ @ 25C Units V V V V V V V V V V V V V V IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH = -7 mA Conditions IIN <250 A IIN <250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes
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Zilog TA = 0C to +70C Sym VOL1 VOL2* Parameter Output Low Voltage Output Low Voltage VCC 2.0V 3.9V 2.0V 3.9V VOL2 Output Low Voltage(P36, P37,P00,P01) Reset Input High Voltage Reset Input Low Voltage 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 0.8 VCC 0.8 VCC VSS - 0.3 VSS - 0.3 Min Max 0.4 0.4 0.8 0.8 0.8 0.8 VCC VCC 0.2 VCC 0.2 VCC 25 25 -1 -1 -1 -1 1 1 1 1 -230 -400 10 15 250 850 Typ @ 25C 0.1 0.2 0.5 0.3 0.3 0.2 1.5 2.0 0.5 0.9 10 10 <1 <1 <1 <1 -50 -90 4 10 100 500 Units V V V V V V V V V V mV mV A A A A A A mA mA A A
Z86C72/C92/L72/L92 IR Microcontroller
Conditions IOL = 1.0 mA IOL = 4.0 mA IOL = 5.0 mA IOL = 7.0 mA IOL = 10 mA IOL = 10 mA
Notes
1
VRH VRl VOFFSET IIL IOL IIR ICC
Comparator Input 2.0V Offset Voltage 3.9V Input Leakage Output Leakage 2.0V 3.9V 2.0V 3.9V
VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV VIN = OV @ 8.0 MHz @ 8.0 MHz @ 32 kHz @ 32 kHz 1,2 1,2 1,2,8
Reset Input Pull- 2.0V Up Current 3.9V Supply Current 2.0V 3.9V 2.0V 3.9V
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Z86C72/C92/L72/L92 IR Microcontroller TA = 0C to +70C Sym ICC1 Parameter Standby Current (WDT Off) VCC 2.0V Min Max 3
Zilog
Typ @ 25C 1 Units mA Conditions HALT Mode VIN = OV, VCC @ 8.0 MHz HALT Mode VIN = OV, VCC @ 8.0 MHz Clock Divide-by16 @ 8.0 MHz Clock Divide-by16 @ 8.0 MHz STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running Notes 1,2
3.9V
5
4
mA
1,2
2.0V 3.9V ICC2 Standby Current 2.0V
2 4 8
0.8 2.5 2
mA mA A
1,2 1,2 3,5
3.9V
10
3
A
3,5
2.0V
500
310
A
3.9V
800
600
A
TPOR VRAM VLV (VBO)
Notes:
Power-On Reset Static RAM Data Retention Voltage VCC Low Voltage Protection ICC1 Crystal/Resonator External Clock Drive
2.0V 3.9V Vram
12 5 0.8
75 20
18 7 0.5 1.7 Frequency 8.0 MHz 8.0 MHz
ms ms V V 8 MHz max Ext. CLK Freq.
6 4
2.15 Typ 3.0 mA 0.3 mA Max 5 5 Unit mA mA
1. All outputs unloaded, inputs at rail 2. CL1 = CL2 = 100 pF 3. Same as note [4] except inputs at V CC 4. The VLV increases as the temperature decreases 5. Oscillator stopped 6. Oscillator stops when VCC falls below VLV limit 7. 32 kHz clock driver input * All Outputs excluding P00, P01, P36, and P37
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Z86C72/C92/L72/L92 IR Microcontroller
DC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS)
Preliminary TA = 0C to +70C Sym Parameter Max Input Voltage VCH Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37) Output Low Voltage Output Low Voltage Output Low Voltage (P00, P01, P36,P37) Reset Input High Voltage Reset Input Low Voltage VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 3.9 V 4.5V 5.5V 0.9 VCC 0.9 VCC VSS - 0.3 VSS -0.3 0.7 VCC 0.7 VCC VSS - 0.3 VSS - 0.3 VCC - 0.4 VCC - 0.4 VCC - 0.8 VCC - 0.8 0.4 0.4 0.8 0.8 0.8 0.8 0.1 0.2 0.3 0.4 0.3 0.2 Min Max 7 7 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC VCC + 0.3 VCC + 0.3 0.5Vcc 0.5Vcc 0.5Vcc 0.5Vcc 4.4 5.4 Typ @ 25C Units V V V Conditions IIN 250 A IIN 250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes
1
VCL
V
VIH
V
VIL VOH1 VOH2
V V V V V V V V V IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH = -7 mA IOL = 1.0 mA IOL = 4.0 mA IOL = 5.0 mA IOL = 7.0 mA IOL = 10 mA
VOL1 VOL2* VOL2
VRH VRl
4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V
0.8 VCC 0.8 VCC VSS - 0.3 VSS - 0.3
VCC VCC 0.2 VCC 0.2 VCC 25 25
2.5 3.0 0.5 0.9 10 10 <1 <1 <1 <1
V V
VOFFSET Comparator Input Offset Voltage IIL Input Leakage IOL IIR ICC Output Leakage Reset Input Current Supply Current WDT Off
mV mV A A A A A A mA mA A A VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
-1 -1 -1 -1
1 1 1 1 -500 -800 20 30 1000 1250
@8.0 MHz @8.0 MHz @ 32 kHz @ 32 kHz
1,2 1.2 1,2,8 1,2,8
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Z86C72/C92/L72/L92 IR Microcontroller
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DC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS) (Continued)
TA = 0C to +70C Sym ICC1 Parameter Standby Current (WDT Off) VCC 4.5V Min Max 6 Typ @ 25C 2 Units mA Conditions HALT Mode VIN = OV, VCC @ 8.0 MHz HALT Mode VIN = OV, VCC @ 8.0 MHz Clock Divide-by16 @ 8.0 MHz Clock Divide-by16 @ 8.0 MHz STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running Notes 1,2
5.5V 4.5V 5.5V
8 5 7
5 1.0 3.0
mA mA mA
1,2 1,2 1,2
ICC2
Standby Current
4.5V
8
2
A
3,5
5.5V 4.5V 5.5V
10 500 800
3 310 600
A A A
3,5 3,5
TPOR VRAM VLV (VBO)
Notes:
Power-On Reset Static RAM Data Retention Voltage VCC Low Voltage Protection ICC1 Crystal/Resonator External Clock Drive
4.5V 5.5V Vram
5.0 4.0 0.8
75 20
8.0 6.0 0.5 1.7 Frequency 8.0 MHz 8.0 MHz
ms ms V V 8 MHz max Ext. CLK Freq.
6 4
2.15 Typ 3.5 mA 0.8 mA Max 5 5 Unit mA mA
1. All outputs unloaded, inputs at rail 2. CL1 = CL2 = 100 pF 3. Same as note [4] except inputs at V CC 4. The VLV increases as the temperature decreases 5. Oscillator stopped 6. Oscillator stops when VCC falls below VLV limit 7. 32 kHz clock driver input * All Outputs excluding P00, P01, P36, and P37
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Z86C72/C92/L72/L92 IR Microcontroller
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
1
R//W
13 12 19
Port 0, /DM
16 18 3
20
Port 1
A7 - A0
1 2
D7 - D0 IN
9
/AS
8 4 5 6 11
/DS (Read)
17
10
Port 1
A7 - A0
14
D7 - D0
OUT
15 7
/DS (Write)
Figure 7. External I/O or Memory Read/Write Timing
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AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary External I/O or Memory Read and Write Timing Table TA = 0C to +70C 8.0MHz No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) TdDS(DM) ThDS(A) Parameter Address Valid to /AS Rising Delay /AS Rising to Address Float Delay /AS Rising to Read Data Required Valid /AS Low Width Address Float to /DS Falling /DS (Read) Low Width /DS (Write) Low Width /DS Falling to Read Data Required Valid Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay /DS Rising to R//W Not Valid Write Data Valid to /DS Falling (Write) Delay /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid /AS Rising to /DS Falling Delay /DM Valid to /AS Falling Delay /DS Rise to /DM Valid Delay /DS Rise to Address Valid Hold Time VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V Min 55 55 70 70 400 400 80 80 0 0 300 300 165 165 260 260 0 0 85 95 60 70 70 70 70 70 80 80 70 80 475 475 100 100 55 55 70 70 70 70 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 2 2 1,2 2
1,2 1,2 1,2 2 2 2 2 2 2 2 1,2 2 2
Notes: 1. When using extended memory timing add 2 TpC 2. Timing numbers given are for minimum TpC
Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0
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Z86C72/C92/L72/L92 IR Microcontroller
AC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS)
Preliminary External I/O or Memory Read and Write Timing Table TA = 0C to +70C 16.0 MHz No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS Td TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) Parameter Address Valid to /AS Rising Delay /AS Rising to Address Float Delay /AS Rising to Read Data Required Valid /AS Low Width Address Float to /DS Falling /DS (Read) Low Width /DS (Write) Low Width /DS Falling to Read Data Required Valid Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay /DS Rising to /AS VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min 25 25 35 35 180 180 40 40 0 0 135 135 80 80 75 75 0 0 50 50 35 35 25 25 35 35 25 25 35 35 230 230 45 45 30 30 70 70 70 70 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 2 1,2 2
1
1,2 1,2 1,2 2 2 2 2 2 2
15 16 17 18 19 20
R//W Valid to /AS Rising Delay TdDS(R/W) /DS Rising to R//W Not Valid TdDW(DSW) Write Data Valid to /DS Falling (Write) Delay TdDS(DW) /DS Rising to Write Data Not Valid Delay TdA(DR) Address Valid to Read Data Required Valid TdAS(DS) /AS Rising to /DS Falling Delay TdM(AS) /DM Valid to /AS Falling Delay TdDS(DM) /DS Rise to /DM Valid Delay ThDS(A) /DS Rise to Address Valid Hold Time
2 1,2 2 2
Notes: 1. When using extended memory timing add 2 TpC. 2. Timing numbers given are for minimum TpC. Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
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Z86C72/C92/L72/L92 IR Microcontroller
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AC CHARACTERISTICS
Additional Timing Diagram
1
3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ
N
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Figure 8. Additional Timing
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Z86C72/C92/L72/L92 IR Microcontroller
AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary Additional Timing Table TA = 0C to +70C 8.0MHz No 1 2 3 4 5 6 7 8A 8B 9 10 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Twsm Sym Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timers Interrupt Request Low Time Interrupt Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V Min 121 121 Max DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1,3 1,3 1,2 1,2 7 7 6 6 4 4
1
37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5 TpC 5 TpC 5TpC 5TpC 75 20 150 40 300 80 1200 320
ns ns ns ns
ns ns ns ns
11 12
Tost Twdt
Oscillator Start-Up Time Watch-Dog Timer Delay Time (5 ms) (10 ms) (20 ms) (80 ms)
12 5 25 10 50 20 225 80
ms ms ms ms ms ms ms ms
Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. Interrupt request through Port 3 (P30). 4. SMR bit D5 = 0
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
AC CHARACTERISTICS(Z86C72/C92 SPECIFICATIONS)
Preliminary Additional Timing Table TA = 0C to +70C 16.0 MHz No 1 2 3 4 5 6 7 8A 8B 9 10 Symbol TpC TrC, TfC TwC TwTinL TwTinH TpTin TrTin, TfTin TwIL TwIL TwIH Twsm Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise Interrupt Request Low Time Int. Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec Oscillator Start-up Time Watch-Dog Timer Delay Time (2.0 ms) 4.0 ms 8.0 ms 32 ms VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min 63 63 Max DC DC 15 15 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1,3 1,3 1,2 1,2 8 8 7 7 4 4 D0=0, 5 D1=0, 5 D0=1, 5 D1=0, 8 D0=1, 5 D1=0, 8 D0=1, 5 D1=0, 8
31 31 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 5TpC 5TpC 2.0 2.0 4.0 4.0 8.0 8.0 32 32
ns ns ns ns
ns ns
11 12
Tost Twdt
ms ms ms ms ms ms ms ms
Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. Interrupt request through Port 3 (P30). 4. SMR bit D5 = 0 5. Reg. WDTMR bit D0=1 6. Reg. SMR bit D5 = 0 7. Reg. SMR bit D5 = 1 8. Reg. WDTMR bit D1-0
6-18
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DS97LVO0900
Zilog
Z86C72/C92/L72/L92 IR Microcontroller
AC CHARACTERISTICS
Handshake Timing Diagrams
1
Data In Data In Valid
2 1 3
Next Data In Valid
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Figure 9. Port I/O with Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Figure 10. Port I/O with Output Handshake Timing
DS97LVO0900
PRELIMINARY
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)
Preliminary Handshake Timing Table TA = 0C to +70C No 1 2 3 4 5 6 7 8 9 10 11 Sym TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDYO(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Falling to RDY Falling Delay DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay RDY Falling to DAV Rising Delay RDY Width RDY Rising to DAV Falling Delay VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V Min 0 0 0 0 155 110 160 115 120 80 0 0 63 63 0 0 160 115 110 80 110 80 Max Data Direction IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
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DS97LVO0900
Zilog
Z86C72/C92/L72/L92 IR Microcontroller
AC CHARACTERISTICS(Z86C72/C92 SPECIFICATIONS)
Preliminary Handshake Timing Table TA = 0C to +70C 16.0 MHz No 1 2 3 4 5 6 7 8 9 10 11 Symbol TSD(DAV) ThD(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY)(DAV) TdD0(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data in Setup Time Data in Hold Time Data Available Width DAV Falling to RDY Falling Delay DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay RDY Falling to DAV RDY Width RDY Rising to DAV Falling Dealy VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V Min 0 0 160 115 155 110 160 115 120 80 0 0 31 31 0 0 160 115 110 80 110 80 Max Data Direction IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
1
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PRELIMINARY
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
PIN FUNCTIONS
/DS (Output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (Output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write. XTAL1 Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network or an external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output. R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory. R//RL (input). This pin, when connected to GND, disables the internal ROM and forces the device to function as a ROMless Z8. (Note that, when left unconnected or pulled high to VCC, the part functions normally as a Z8 ROM version.) Port 0 (P07-P00). Port 0 is an 8-bit, bi-directional, CMOS compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The output drivers are push-pull. Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0. Handshake signal direction is dictated by the I/O direction to Port 0 of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble. For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. Port 0 is set in the high-impedance mode (if selected as an address output) along with Port 1 and the control signals /AS, /DS, and R//W through P3M bits D4 and D3(Figure 11). A ROM mask option is available to program 0.4 VDD CMOS trip inputs on P00-P03 of the L72. This allows direct interface to mouse/trackball IR sensors. An optional 200 kOhm pull-up is available as a mask option on all Port 0 bits with nibble select. These pull-ups are disabled when configured (bit by bit) as an output.
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DS97LVO0900
Zilog
Z86C72/C92/L72/L92 IR Microcontroller
1
4 Port 0 (I/O or A15 - A8) Z86LXX MCU 4
Optional Handshake Controls /DAV0 and RDY0 (P32 and P35)
OEN
Mask Option 200 k PAD
Out
In
In Refer to the Z86C17 specification for application information in utilizing these inputs in a mouse or trackball application.
0.4 VDD Trip Point Buffer
Figure 11. Port 0 Configuration
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
PIN FUNCTIONS (Continued)
Port 1 (P17-P10). Port 1 is a multiplexed Address (A7-A0) and Data (D7-D0), CMOS compatible port. Port 1 is dedicated to the Zilog ZBus(R)-compatible memory interface. The operations of Port 1 are supported by the Address Strobe (/AS) and Data Strobe (/DS) lines, and by the Read/Write (R//W) and Data Memory (/DM) control lines. Data memory read/write operations are done through this port (Figure 12). If more than 256 external locations are required, Port 0 outputs the additional lines. Port 1 can be placed in the high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the Z86L/CX2 to share common resources in multiprocessor and DMA applications. Port1 can also be configured for standard port output mode.
8 Z86LXX MCU
Port 1 (I/O or AD7 - AD0)
Optional Handshake Controls /DAV1 and RDY1 (P33 and P34)
OEN
PAD
Out
In
Auto Latch
R 500 K
Figure 12. Port 1 Configuration
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DS97LVO0900
Zilog Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS compatible I/O port. These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight 200 kOhms (50%) pull-up resistors on this port. Bits programmed as outputs are globally programmed as either push-pull or opendrain. Port 2 may be placed under handshake control. In this configuration, Port 3 lines, P31 and P36 are used as the handshake controls lines /DAV2 and RDY2. The hand-
Z86C72/C92/L72/L92 IR Microcontroller shake signal assignment for Port 3, lines P31 and P36 is dictated by the direction (input or output) assigned to Bit 7, Port 2 (Figure 13). The eight bits of Port 2 are configured as inputs with open-drain outputs. Port 2 also has an 8-bit input OR and an AND gate which can be used to wake up the part (Figure 39). P20 can be programmed to access the edge selection circuitry (Figure 22).
1
Port 2 (I/O) Z86LXX MCU
Optional Handshake Controls /DAV2 and RDY2 (P31 and P36)
VCC Open-Drain 200 k OEN Mask Option PAD
Out
In
Figure 13. Port 2 Configuration
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
PIN FUNCTIONS (Continued)
Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible three fixed input and four fixed output port. Port 3 consists of three fixed input (P33-P31) and four fixed output (P37P34), and can be configured under software control for Input/Output, Interrupt, Port handshake, Data Memory functions and output from the counter/timers. P31, P32, and P33 are standard CMOS inputs; outputs are push-pull. Two on-board comparators process analog signals on P31 and P32 with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the Counter Timer edge detection circuit is through P31 or P20 (see CTR1 description). Port 3 provides the following control functions: handshake for Ports 0, 1, and 2 (/DAV and RDY); three external interrupt request signals (IRQ2-IRQ0); Data Memory Select (/DM) (Table 2). Port 3 also provides output for each of the counter/timers and the AND/OR Logic. Control is performed by programming bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2.
Table 2. Pin Assignments Pin Pref1 P31 P32 P33 P34 P35 P36 P37 P20 I/O IN IN IN IN OUT OUT OUT OUT I/O C/T IN Comp. RF1 AN1 AN2 RF2 A01 Int. IRQ2 IRQ0 IRQ1 P0 HS P1 HS P2 HS D/R D/R D/R R/D R/D R/D A02 IN DM Ext
T8 T16 T8/16
Notes: HS = Handshake Signals D = /DAV R = RDY
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Z86C72/C92/L72/L92 IR Microcontroller
Counter/Timer T8 P34 OUT P34 OUT P31 + CTR0 D0
P34 PAD
1
Pref1
0 Normal Control 1 8-bit Timer output active P37
P37 OUT P32 + -
PAD
P33 (Pref2) PCON D0 0 = P34, P37 Standard Output * 1 = P34, P37 Comparator Output
*
Reset condition.
Figure 14. Port 3 Configuration
Comparator Inputs. In Analog Mode, Port 3 (P31 and P32) have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 is diverted to the SMR Sources (excluding P31, P32, and P33) as shown in Figure 38. In digital mode, P33 is used as D3 of the Port 3 input register which then generates IRQ1 as shown in Figure 15. When P31 is used as a counter timer input (demodulation mode), Timer input is always taken from the P31 digital input buffer (whether or not analog mode is enabled).
Notes: Comparators are powered down by entering STOP mode. For P31-P33 to be used as a Stop-Mode Recovery source, these inputs must be placed into digital mode. Comparator Outputs. These may be programmed to be output on P34 and P37 through the PCON register (Figure 15).
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
PIN FUNCTIONS (Continued)
/RESET (Input, active Low). Initializes the MCU. Reset is accomplished either through Power-On, Watch-Dog Timer, Stop-Mode Recovery, Low Voltage detection, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin Low for the POR time. Any devices driving the reset line should be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. There is no internal condition that will not allow an external reset to occur. After the POR time, /RESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z86L/CX2 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-10 TpC cycles after the RST is released. For Power-On Reset, the typical reset output time is 5 ms. The Z86L/CX2 does not reset WDTMR, SMR, P2M, P2, P3, or P3M registers on a Stop-Mode Recovery operation.
Pref1 200 K P31 P32 Z86L7X MCU P33 P34 P35 P36 P37 Note: P31, 32, 33 have a 200 K mask option. Port 3 (I/O or Handshake) Mask Option
R247 = P3M D1 1 = Analog 0 = Digital
DIG. P31 (AN1) + Pref1* Comp1 AN. IRQ2, P31 Data Latch
P32 (AN2) + P33 (REF2) -
Comp2
IRQ0, P32 Data Latch
From Stop-Mode Recovery Source of SMR
IRQ1, P33 Data Latch
Figure 15. Port 3 Configuration 6-28 PRELIMINARY DS97LVO0900
Zilog
Z86C72/C92/L72/L92 IR Microcontroller
CTR0, D0
VDD
1
Pad P34
Out 34 T8_Out
MUX
CTR2, D0
VDD
Out 35 MUX T16_Out Pad P35
CTR1, D6
VDD
Out 36 T8/16_Out MUX Pad P36
Figure 16. Port 3 Configuration
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
FUNCTIONAL DESCRIPTION
The Z8(R) incorporates special functions to enhance functionality in consumer and battery operated applications. Reset. The device is reset in one of the following conditions: 1. Power-On Reset 2. Watch-Dog Timer 3. Stop-Mode Recovery Source 4. Low Voltage Detection 5. External Reset Program Memory. The Z86L/C72 addresses up to 16K of internal program memory, with the remainder being external memory (Figure 17). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain five 16-bit vectors that correspond to the five available interrupts. At addresses 16K and greater, the Z86L/C72 executes external program memory fetches (refer to external memory timing specifications). The Z86L72/C92 addresses up to (64K - 512 KB) of external program memory beginning at address 0. This is also true of the Z86L/C72 when the R//RL input is forced to a low. RAM. The Z86L72 has a 768-byte RAM. 256 bytes make up the Register file. The remaining 512 bytes make up the Extended Data RAM. Extended Data RAM. The Extended Data RAM occupies the address range FE00H-FFFFH (512 bytes). This range of external addresses is replaced by the internal Extended Data RAM and cannot be used to directly write to or read from External Memory. Accessing the Extended Data RAM is accomplished by using LDE, LDEI, LDC, or LDCI instructions. Port 1 and Port 0 are free to be set as I/O or ADDR/DATA modes (except for high-impedance) when accessing Extended Data RAM. In addition, if the External Memory uses the same address range as the Extended Data RAM, it can be used as the External Stack only. Note: The Extended Data RAM cannot be used as STACK or instruction/code memory. Accessing the Extended Data RAM has the following condition: P01M register bits D4-D3 cannot be set to 11.
External ROM 16384 Location of First Byte of Instruction Executed After RESET 12 11 10 9 8 7 Interrupt Vector (Lower Byte) 6 5 4 3 2 1 0 On-Chip ROM Reset Start Address Reserved Reserved IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Interrupt Vector (Upper Byte)
Figure 17. L72/C72 Program Memory Map
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Zilog
Z86C72/C92/L72/L92 IR Microcontroller Expanded Register File. The register file has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices into the register address area. The Z8 register address space R0 through R15 has been implemented as 16 groups of 16 registers per group. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register file bank. Note that expanded register bank is also referred to as expanded register group (Figure 19). The upper nibble of the register pointer (Figure 21) selects which working register group of 16 bytes in the register file, out of the possible 256, will be accessed. The lower nibble selects the expanded register file bank and, in the case of the Z86L/CX2 family, banks 0, F, and D are implemented. A 0H in the lower nibble will allow the normal register file (bank 0) to be addressed, but any other value from 1H to FH will exchange the lower 16 registers to an expanded register bank (See Figure 19).
Z86L72 and Z86E72 versions
65535
1
External Data Memory
16,384
For example: R253 RP = 00H R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if:
Not Addressable
0
Figure 18. Data Memory Map External Memory (/DM). The Z86L72 addresses up to 48K bytes (minus Extended Data RAM space) of external memory beginning at address 16384 (Figure 18). External data memory is included with, or separated from, the external program memory space. /DM, an optional I/O function that is programmed to appear on P34, is used to distinguish between data and program memory space. The state of the /DM signal is controlled by the type of instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references data (/DM active Low) memory.
R253 RP = 0DH R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved The counter/timers are mapped into ERF group D. Access is easily done using the following example: LD LD LD LD RP, #0DH Select ERF D for access to bank D( working register group 0) R0,#xx R1, #xx R1, 2 Load CTRL0 Load CTRL1 CTRL2 CTRL1
LD LD LD
RP, #7DH Select expanded register bank D and working register group 7 of bank 0 for access . 71H, R2 R1, R2 CTRL2 register 71H CTRL2 register 71H
DS97LVO0900
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Z8(R) ST ANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER** REGISTER POINTER
7 6 5 4 3 2 1 0 FF FE FD SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M Reserved Reserved Reserved Reserved Reserved Reserved U U 0 U 0 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0 U U 0 U U 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0
Working Register Group Pointer
Expanded Register Bank/Group Pointer
FC FB FA F9 F8
* *
Z8 Register File (Bank0) **
FF FO
F7 F6 F5 F4 F3 F2 F1 F0
EXP ANDED REG. BANK/GROUP (F) REGISTER** RESET CONDITION
*
7F Reserved
(F) 0F (F) 0E (F) 0D (F) 0C
WDTMR Reserved SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON
U
U
U
0
1
1
0
1
U
0
U
0
0
0
U
U
(F) 0B (F) 0A (F) 09 (F) 08
0
0
1
0
0
0
U
0
Reserved
0F 00
(F) 07 (F) 06 (F) 05 (F) 04 (F) 03 (F) 02 (F) 01
*
(F) 00
U
U
U
U
U
U
U
0
EXPANDED REG. BANK/GROUP (D) REGISTER** RESET CONDITION Reserved HI8 L08 HI16 L016 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0 0 0 0 U 0 U U U U U U U U U U U U U U U U 0 U 0 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U
EXP ANDED REG. GROUP (0) REGISTER** RESET CONDITION
P3 P2 P1 P0 0 U U U 0 U U U 0 U U U 0 U U U U U U U U U U U U U U U U U U U
(D) 0C (D) 0B (D) 0A (D) 09 (D) 08 (D) 07 (D) 06 (D) 05 (D) 04 (D) 03 (D) 02 (D) 01 (D) 00
* *
(0) 03 (0) 02 (0) 01 (0) 00 U = Unknown
* Will not be reset with a Stop-Mode Recovery ** All addresses are in Hexadecimal
Will not be reset with a Stop-Mode Recovery, except Bit 0.
6-32
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DS97LVO0900
Zilog
Z86C72/C92/L72/L92 IR Microcontroller Note: When SPH is used as a general-purpose register and Port 0 is in address mode, the contents of SPH will be loaded into Port 0 whenever the internal stack is accessed.
Expanded Register File Pointer Working Register Pointer
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
1
Default Setting After Reset = 0000 0000
r7 r 6 r5 r 4
r
3
r
2
r
1
r
0
R253
Figure 20. Register Pointer Register File. The register file (bank 0) consists of four I/O port registers, 236 general-purpose registers, and 16 control and status registers (R0-R3, R4-R239, and R240R255, respectively), Plus two expanded registers groups (Banks D and F). Instructions can access registers directly or indirectly through an 8-bit address field. This allows a short, 4-bit register address using the Register Pointer (Figure 23). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note: Working register group E0-EF can only be accessed through working registers and indirect addressing modes. Stack. The Z86L/CX2 external data memory or the internal register file is used for the stack. An 8-bit Stack Pointer (R255) is used for the internal stack that resides in the general-purpose registers (R4-R239). SPH is used as a general-purpose register only when using internal stacks.
The upper nibble of the register file address provided by the register pointer specifies the active working-register group
FF R15 to R0 F0
Specified Working Register Group
2F 20 1F Register Group 1 10 0F Register Group 0 I/O Ports
The lower nibble of the register file address provided by the instruction points to the specified register
R15 to R0
R15 to R4 R3 to R0
00
Figure 21. Register Pointer
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Z86C72/C92/L72/L92 IR Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued) Counter/Timer Register Description
Expanded Register Group D (D)H0C (D)H0B (D)H0A (D)H09 (D)H08 (D)H07 (D)H06 (D)H05 (D)H04 (D)H03 (D)H02 (D)H01 (D)H00 Reserved HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0 HI16(D)H09: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the MSByte of the data. Bit Position 76543210 R W
Field T16_Capture_HI
Description Captured Data No Effect
L016(D)H08: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the LSByte of the data. Bit Position 76543210 R W
Field T16_Capture_LO
Description Captured Data No Effect
HI8(D)H0B: Holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 1. Field T8_Capture_HI Bit Position 76543210 Description R Captured Data W No Effect
TC16H(D)H07: Counter/Timer2 MS-Byte Hold Register. Bit Position 76543210 R W
Field T16_Data_HI
Description Data
L08(D)H0A: Holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 0. Field T16_Capture_LO Bit Position 76543210 Description R Captured Data W No Effect
TC16L(D)H06: Counter/Timer2 LS-Byte Hold Register. Bit Position 76543210 R/W
Field T16_Data_LO
Description Data
TC8H(D)H05: Counter/Timer8 High Hold Register. Field T8_Level_HI Bit Position 76543210 R/W Description Data
TC8L(D)H04: Counter/Timer8 Low Hold Register. Field T8_Level_LO Bit Position 76543210 R/W Description Data
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DS97LVO0900
Zilog CTR0 (D)00H: Counter/Timer8 Control Register. Field T8_Enable Bit Position 7------R W Single/Modulo-N Time_Out -6-------5----R/W R W T8_Clock ---43--R/W Value 0* 1 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 0* 1
Z86C72/C92/L72/L92 IR Microcontroller
Description Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disabled Data Capture Int. Enable Data Capture Int. Disable Data Capture Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34
1
Capture_INT_Mask Counter_INT_Mask P34_Out
Note: *Indicates the value upon Power-On Reset.
-----2-------1-------0
R/W R/W R/W
CTR0: Counter/Timer8 Control Register Description T8 Enable. This field enables T8 when set (written) to 1. Single/Modulo-N. When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Time-Out. This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to this location. This is the only way to reset this status condition, therefore, care should be taken to reset this bit prior to using/enabling the counter/timers. Note: Care must be taken when utilizing the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers will be ORed or ANDed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a reset condition will occur.
T8 Clock. Defines the frequency of the input signal to T8. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask. Set this bit to allow interrupt when T8 has a time out. P34_Out. This bit defines whether P34 is used as a normal output pin or the T8 output.
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FUNCTIONAL DESCRIPTION (Continued)
CTR1(D)H01: Controls the functions in common with the T8 and T16. Field Mode P36_Out/ Demodulator_Input Bit Position 7-------6-----R/W R/W 0* 1 0 1 T8/T16_Logic/ Edge _Detect --54---R/W 00 01 10 11 00 01 10 11 Transmit_Submode/Glitch_Filter ----32-R/W 00 01 10 11 00 01 10 11 Initial_T8_Out/ Rising_Edge ------1R/W 0 1 0 1 0 1 Initial_T16_Out/ Falling _Edge -------0 R/W 0 1 0 1 0 1 Value 0* 1 Description Transmit Mode Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit Mode Normal Operation Ping-Pong Mode T16_Out=0 T16_Out=1 Demodulation Mode No Filter 4 SCLK Cycle 8 SCLK Cycle 16 SCLK Cycle Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0
R W
Note: *Indicates the value upon Power-On Reset
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Zilog CTR1 Register Description Mode. If it is 0, the Counter/Timers are in the transmit mode, otherwise they are in the demodulation mode. P36_Out/Demodulator_Input. In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/Timers is from P20 or P31. T8/T16_Logic/Edge _Detect. In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter. In Transmit Mode, this field defines whether T8 and T16 are in the "Ping-Pong" mode or in independent normal operation mode. Setting this field to "Normal Operation Mode" terminates the "PingPong Mode" operation. When set to 10, T16 is immediately forced to a 0. When set to 11, T16 is immediately forced to a 1.
Z86C72/C92/L72/L92 IR Microcontroller In Demodulation Mode, this field defines the width of the glitch that should be filtered out. Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When this bit is set to 1 or 0, T8_OUT will be set to the opposite state of this bit. This insures that when the clock is enabled a transition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). When this bit is set, T16_OUT will be set to the opposite state of this bit. This insures that when the clock is enabled a transition occurs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Note: Modifying CTR1, (D1 or D0) while the counters are enabled will cause un-predictable output from T8/16_OUT.
1
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FUNCTIONAL DESCRIPTION (Continued)
CTR2 (D)H02: Counter/Timer16 Control Register. Field T16_Enable Bit Position 7------R W Single/Modulo-N -6-----R/W 0 1 0 1 0 1 0 1 00 01 10 11 0 0 1 0* 1 Value 0* 1 0 1 Description Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P35 as Port Output T16 Output on P35
Time_Out
--5-----
R
T16 _Clock
---43---
W R/W
Capture_INT_Mask Counter_INT_Mask P35_Out
-----2-------1-------0
R/W R/W R/W
Notes: * Indicates the value upon Power-On Reset CTR2 Description T16_Enable. This field enables T16 when set to 1. Single/Modulo-N. In Transmit Mode, when set to 0, the counter reloads the initial value when terminal count is reached. When set to 1, the counter stops when the terminal count is reached. In Demodulation Mode, when set to 0 , T16 captures and reloads on detection of all the edges; when set to 1, T16 captures and detects on the first edge, but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode. Time_Out. This bit is set when T16 times out (terminal count reached). In order to reset it, a 1 should be written to this location. T16_Clock. Defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into LO16 and HI16. Counter_INT_Mask. Set this bit to allow interrupt when T16 times out. P35_Out. This bit defines whether P35 is used as a normal output pin or T16 output.
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Z86C72/C92/L72/L92 IR Microcontroller
Counter/Timer Functional Blocks
CTR1 D5,D4
1
Edge Detector Pos Edge Neg Edge
P31 MUX P20
Glitch Filter
CTR1 D6 CTR1 D3,D2
Figure 22. Glitch Filter Circuitry
Z8 Data Bus CTR0 D2 Pos Edge Neg Edge HI8 CTR0 D4, D3 Clock LO8 IRQ4
CTR0 D1 Clock Select 8-Bit Counter T8
SCLK
T8_OUT
TC8H
TC8L
Z8 Data Bus
Figure 23. 8-Bit Counter/Timer Circuits
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FUNCTIONAL DESCRIPTION (Continued)
Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5-D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal which have a width less than specified (CTR1 D3, D2) are filtered out. T8 Transmit Mode When T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0. When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If the initial value (CTR1 D1) is 0, TC8L is loaded, otherwise TC8H is loaded into the counter. In Single-Pass Mode (CTR0 D6), T8 counts down to 0 and stops, T8_OUT toggles, the time-out status bit (CTR0 D5) is set, and a time-out interrupt can be generated if it is enabled (CTR0 D1) (Figure 24). In Modulo-N Mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. Then T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5) and generates an interrupt if enabled (CTR0 D1) (Figure 25). This completes one cycle. T8 then loads from TC8H or TC8L according to the T8_OUT level, and repeats the cycle. The user can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Care must be taken not to write these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. An initial count of 1 is not allowed (a non-function will occur). An initial count of 0 will cause TC8 to count from 0 to %FF to %FE (Note, % is used for hexadecimal values). Transition from 0 to %FF is not a time-out condition. Note: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands, first stopping the counter/timers, then resetting the status bits is necessary. This is required because it takes one counter/timer clock interval for the initiated event to actually occur.
TC8H Counts
"Counter Enable" Command, T8_OUT Switches To Its Initial Value (CTR1 D1)
T8_OUT Toggles, Time-Out Interrupt
Figure 24. T8_OUT in Single-Pass Mode
T8_OUT Toggles
T8_OUT
TC8L
TC8H
TC8L
TC8H
TC8L
"Counter Enable" Command, T8_OUT Switches To Its Initial Value (CTR1 D1)
Time-Out Interrupt
Time-Out Interrupt
Figure 25. T8_OUT in Modulo-N Mode
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Zilog T8 Demodulation Mode The user should program TC8L and TC8H to %FF. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1 D5, D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the current value of T8 is one's complemented and put into one of the capture registers. If it is a positive edge, data is
Z86C72/C92/L72/L92 IR Microcontroller put into LO8, if negative edge, HI8. One of the edge detect status bits (CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2). Meanwhile, T8 is loaded with %FF and starts counting again. Should T8 reach 0, the time-out status bit (CTR0 D5) is set, an interrupt can be generated if enabled (CTR0 D1), and T8 continues counting from %FF (Figure 26).
1
T8 (8-Bit) Count Capture
No
T8_Enable (Set By User)
Yes
Edge Present No Yes
What Kind Of Edge Pos Neg
T8 L08
T8 HI8
%FF T8
Figure 26. Demodulation Mode Count Capture Flowchart
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T8 (8-Bit) Transmit Mode
No
T8_Enable Bit Set CTR0, D7 Yes
Reset T8_Enable Bit 0
CTRI, D1 Value
1
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int If Enabled
Enable T8
No
T8_Timeout Yes
Single Pass
Single Pass? Modulo-N
1 T8_OUT Value
0
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Enable T8 Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int If Enabled No
T8_Timeout Yes Disable T8
Figure 27. Transmit Mode Flowchart
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Z86C72/C92/L72/L92 IR Microcontroller
T8 (8-Bit) Demodulation Mode
1
No
T8_Enable CTR0, D7 Yes %FF TC8
Edge Present No Yes
Disable T8
Enable TC8
T8_Enable Bit Set
Yes No Edge Present
Yes Set Edge Present Status Bit And Trigger Data Capture Int. If Enabled
T8 Time Out
No
Yes Set Time-out Status Bit And Trigger Time Out Int. If Enabled
Continue Counting
Figure 28. Demodulation Mode Flowchart
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FUNCTIONAL DESCRIPTION (Continued)
Z8 Data Bus CTR2 D2 Pos Edge Neg Edge HI16 CTR2 D4, D3 Clock 16-Bit Counter T16 LO16 IRQ3
CTR2 D1 Clock Select
SCLK
T16_OUT
TC16H
TC16L
Z8 Data Bus
Figure 29. 16-bit Counter/Timer Circuits
T16 Transmit Mode In Normal or Ping-Pong Mode, the output of T16 when not enabled is dependent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. The user can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3, D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1 D0). When T16 counts down to 0, T16_OUT is toggled (in Normal or Ping-Pong Mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. Note that global interrupts will override this function as described in the interrupts section. If T16 is in Single-Pass Mode, it is stopped at this point. If it is in Modulo-N Mode, it is loaded with TC16H * 256 + TC16L and the counting continues.
The user can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. Care must be taken not to load these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 will cause T16 to count from 0 to %FF FF to %FFFE. Transition from 0 to %FFFF is not a time-out condition.
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Z86C72/C92/L72/L92 IR Microcontroller
TC16H*256+TC16L Counts
1
"Counter Enable" Command, T16_OUT Switches To Its Initial Value (CTR1 D0)
T16_OUT Toggles, Time-Out Interrupt
Figure 30. T16_OUT in Single-Pass Mode
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT
TC16H*256+TC16L
"Counter Enable" Command, T16_OUT Switches To Its Initial Value (CTR1 D0)
T16_OUT Toggles, Time-Out Interrupt
T16_OUT Toggles, Time-Out Interrupt
Figure 31. T16_OUT in Modulo-N Mode
T16 Demodulation Mode The user should program TC16L and TC16H to %FF. After T16 is enabled, when the first edge (rising, falling, or both depending on CTR1 D5, D4) is detected, T16 captures HI16 and LO16 reloads and begins counting. If D6 of CTR2 is 0: When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the current count in T16 is one's complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1 D1, D0) is set and an interrupt is generated if enabled (CTR2 D2). T16 is loaded with %FFFF and starts again.
If D6 of CTR2 is 1: T16 ignores the subsequent edges in the input signal and continues counting down. A time out of T8 will cause T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 will capture and reload on the next edge (rising, falling, or both depending on CTR1 D5, D4) but continue to ignore subsequent edges. Should T16 reach 0, it continues counting from %FFFF; meanwhile, a status bit (CTR2 D5) is set and an interrupt time-out can be generated if enabled (CTR2 D1).
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FUNCTIONAL DESCRIPTION (Continued)
Ping-Pong Mode This operation mode is only valid in Transmit Mode. T8 and T16 need to be programmed in Single-Pass Mode (CTR0 D6, CTR2 D6) and Ping-Pong Mode needs to be programmed in CTR1 D3, D2. The user can begin the operation by enabling either T8 or T16 (CTR0 D1 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled and T16 is enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count it stops, T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1. Note: Enabling Ping-Pong operation while the counter/timers are running may cause intermittent counter/timer function. Disable the counter/timers, then reset the status flags prior to instituting this operation.
Enable TC8
Time-Out
Enable Ping-Pong CTR1 D3,D2 TC16
Time-Out
Figure 32. Ping-Pong Mode
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Zilog To Initiate Ping-Pong Mode First, make sure both counter/timers are not running. Then set T8 into Single-Pass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set Ping-Pong Mode (CTR1 D2, D3). These instructions do not have to be in any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0 D7) or T16 (CTR2 D7).
Z86C72/C92/L72/L92 IR Microcontroller During Ping-Pong Mode The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) will alternately be set and cleared by hardware. The time-out bits (CTR0 D5, CTR2 D5) will be set every time the counter/timers reach the terminal count.
1
TC8H
TC8H T8_OUT Toggles TC16H*256+TC16L
T8_OUT
Enable T8, T8_OUT Switches To Its Initial Value
T8_OUT Toggles
TC16H*256+TC16L T16_OUT Toggles T16_OUT
T16_OUT
T16_OUT Switches To Its Initial Value When TC16 Is Enabled
Figure 33. T8_OUT and T16_OUT in Ping-Pong Mode
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FUNCTIONAL DESCRIPTION (Continued)
P34_INTERNAL MUX
P34_EXT
CTR0 D0 P36_INTERNAL T8_OUT T16_OUT CTR1, D2 AND/OR/NOR/NAND Logic MUX CTR1 D6 CTR1 D5,D4 CTR1 D3 P35_INTERNAL MUX P35_EXT MUX P36_EXT
CTR2 D0
Figure 34. Output Circuit
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Zilog Interrupts. The Z86L7X/CX2 has five different interrupts. The interrupts are maskable and prioritized (Figure 35). The five sources are divided as follows: three sources are claimed by Port 3 lines P33-P31, the remaining two by the
Z86C72/C92/L72/L92 IR Microcontroller counter/timers (Table 3). The Interrupt Mask Register globally or individually enables or disables the five interrupt requests.
1
IRQ0 IRQ 1, 3, 4
IRQ2
Interrupt Edge Select
IRQ Register (D6, D7)
IRQ
IMR 5 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 35. Interrupt Block Diagram
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FUNCTIONAL DESCRIPTION (Continued)
Table 3. Interrupt Types, Sources, and Vectors Name IRQ0 Source /DAV0, IRQ0 Vector Location 0, 1 Comments External (P32), Rising Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising Falling Edge Triggered Internal Internal Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6 . The configuration is shown in Table 4. Table 4. IRQ Register IRQ D7 0 0 1 1 D6 0 1 0 1 Interrupt Edge IRQ2 (P31) F F R R/F IRQ0 (P32) F R F R/F
IRQ1
IRQ1
2, 3
IRQ2
/DAV2, IRQ2, TIN T16 T8
4, 5
IRQ3 IRQ4
6, 7 8, 9
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All Z86L/CX2 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling, or both edge triggered, and are programmable by the user. The software can poll to identify the state of the pin.
Notes: F = Falling Edge R = Rising Edge In analog mode, the Stop-Mode Recovery sources selected by the SMR register are connected to the IRQ1 input. Any of the Stop-Mode Recovery sources for SMR (except P31, P32, and P33) can be used to generate IRQ1 (falling edge triggered)
Clock. The Z86L/CX2 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The Z86L/CX2 onchip oscillator may be driven with a cost-effective RC network or other suitable external clock source. The crystal should be connected across XTAL1 and XTAL2 using the recommended capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 36).
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Zilog Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power Fail to Power OK status.
Z86C72/C92/L72/L92 IR Microcontroller
2. Stop-Mode Recovery (if D5 of SMR = 1). 3. WDT Time-Out. The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC, LC oscillators).
1
XTAL1 C1 C1 L
XTAL1 C1 R
XTAL1 C1 Rf
XTAL1
XTAL1
XTAL2 C2 C2
XTAL2
XTAL2 C2 Rd
XTAL2
XTAL2
Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * f = 8 MHz * Preliminary value including pin parasitics
LC C1, C2 = 22 pF L = 130 H * f = 3 MHz *
RC @ 3V VCC (TYP) C1 = 33 pF * R = 1K *
32 kHz XTAL C1 = 20 pF, C = 33 pF Rd = 56 - 470K Rf =10 M
External Clock
Figure 36. Oscillator Configuration
HALT. HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT.
STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A (typical) or less. STOP mode is terminated only by a reset, such as WDT time-out, POR, SMR, or external reset. This causes the processor to restart the application program at address 000CH. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode = FFH) immediately before the appropriate sleep instruction, i.e., FF 6F or FF 7F NOP HALT ; clear the pipeline ; enter HALT mode NOP STOP ; clear the pipeline ; enter STOP mode
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FUNCTIONAL DESCRIPTION (Continued)
Port Configuration Register (PCON). The PCON register configures the comparator output on Port 3. It is located in the expanded register file at Bank F, location 00 (Figure 37).
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Reserved (Must be 1) * Default Setting After Reset
Figure 37. Port Configuration Register (PCON) (Write Only)
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Zilog Comparator Output Port 3 (D0). Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration. Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 38). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hard-
Z86C72/C92/L72/L92 IR Microcontroller ware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4, of the SMR register, specify the source of the Stop-Mode Recovery signal. Bit D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded Register Group at address 0BH.
1
SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 0 11 P32 100 P33 101 P27 11 0 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * Stop Recovery Level 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery**
* Default Setting After Reset ** Default Setting After Reset and Stop-Mode Recovery
Figure 38. Stop-Mode Recovery Register
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FUNCTIONAL DESCRIPTION (Continued)
SMR D4 D3 D2 000 VCC VCC
SMR2 D4 D3 D2 000
SMR D4 D3 D2 010 P20 P31 S1 P23
SMR2 D4 D3 D2 001
SMR D4 D3 D2 011 P20 P32 S2 SMR D4 D3 D2 100 P33 S3 To IRQ1 S4 SMR D4 D3 D2 101 P27 SMR D4 D3 D2 110 P20 P23 P31 P32 P33 P31 P32 P33 P27
SMR2 D4 D3 D2 010
SMR2 D4 D3 D2 011
SMR2 D4 D3 D2 100
P31 P32 P33 P00 P07
SMR2 D4 D3 D2 101
SMR D4 D3 D2 111 P20 P27 SMR D6
P31 P32 P33 P00 P07
SMR2 D4 D3 D2 110
P31 P32 P33 P20 P21 P22
SMR2 D4 D3 D2 111
To RESET and WDT Circuitry (Active Low)
SMR2 D6
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Zilog SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR controls a Divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0.
Z86C72/C92/L72/L92 IR Microcontroller Stop-Mode Recovery Delay Select (D5). This bit, if Low, disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is one. If the "fast" wake up is selected, the Stop-Mode Recovery source needs to be kept active for at least 5TpC. Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86L/CX2 from STOP mode. A 0 indicates Low level recovery. The default is 0 on POR (Figure 36). Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. It is a Read Only Flag bit. A 1 in D7 (warm) indicates that the device will awaken from a SMR source or a WDT while in STOP mode. A 0 in this bit (cold) indicates that the device will be reset by a POR, WDT while not in STOP, or the device was awakened by a low voltage standby mode. Stop-Mode Recovery Register 2 (SMR). This register determines the mode of the Stop Mode Recovery for SMR2. If SMR2 is used in conjunction with SMR, either of the specified events will cause a Stop-Mode Recovery. Note: Port pins configured as outputs are ignored as a SMR or SMR2 recovery source. For example, if the NAND of P23-20 is selected as the recovery source and P20 is configured as an output then the remaining SMR pins (P23-P21) form the NAND equation.
1
OSC
/2
/ 16
SCLK SMR, D0 TCLK
Figure 40. SCLK Circuit Stop-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR specify the wake up source of the STOP recovery (Figure 39 and Table 5). Table 5. Stop-Mode Recovery Source D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27
P33-P31 cannot wake up from stop mode if the input lines are configured as analog input. Note: Any Port 2 bit defined as an output will drive the corresponding input to the default state to allow the remaining inputs to control the AND/OR function. Refer to SMR2 register for other recover sources.
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FUNCTIONAL DESCRIPTION (Continued)
SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR only* 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level 0 Low* 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events will cause a Stop-Mode Recovery. *Default Setting After Reset
Figure 41. Stop-Mode Recovery Register 2 ((0F) DH: D2-D4, D6 Write Only)
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Zilog Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is selected with bit 4 of the WDT register. Bit 0 and 1 control a tap circuit that determines the
Z86C72/C92/L72/L92 IR Microcontroller time-out period. Bit 2 determines whether the WDT is active during HALT and Bit 3 determines WDT activity during STOP. Bits 5 through 7 are reserved (Figure 42). This register is accessible only during the first 64 processor cycles (128 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a StopMode Recovery (Figure 38). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register Group at address location 0FH. It is organized as follows:
1
WDTMR (0F) 0F D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP 00 01 * 10 11
INT RC OSC External Clock 5 ms 256 TpC 10 ms 512 TpC 20 ms 1024 TpC 80 ms 4096 TpC
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Chip RC * 1 XTAL Reserved (Must be 0) * Default Setting After Reset
Figure 42. Watch-Dog Timer Mode Register (Write Only)
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FUNCTIONAL DESCRIPTION (Continued)
WDT Time Select (D0, D1). Selects the WDT time period. It is configured as shown in Table 6. Table 6. WDT Time Select D1 0 0 1 1 D0 0 1 0 1 Time-Out of Internal RC OSC 5 ms min 10 ms min 20 ms min 80 ms min Time-Out of XTAL Clock 256 TpC 512 TpC 1024 TpC 4096 TpC WDTMR During STOP (D3). This bit determines whether or not the WDT is active during STOP mode. Since the XTAL clock is stopped during STOP mode, the on-board RC has to be selected as the clock source to the WDT/POR counter. A 1 indicates active during STOP. The default is 1. Clock Source for WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator.
Notes: TpC = XTAL clock cycle. The default on reset is 10 ms.
WDTMR During HALT (D2). This bit determines whether or not the WDT is active during HALT mode. A 1 indicates active during HALT. The default is 1.
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Z86C72/C92/L72/L92 IR Microcontroller
/RESET
5 Clock Filter
* /CLR 2 CLK
18 Clock RESET Generator
RESET
1
Internal RESET Active High
WDT TAP SELECT CK Source Select (WDTMR) XTAL INTERNAL RC OSC. Low Operating Voltage Det. M U X POR/WDT 2 3 4 1 CLK WDT/POR Counter Chain /CLR1
VDD VBO/VLV 2V REF .
+ -
WDT From Stop Mode Recovery Source Stop Delay Select (SMR) * /CLR1 and /CLR2 enable the WDT/POR and 18 Clock Reset timers upon a Low to High input translation.
VCC
12 ns Glitch Filter
Figure 43. Resets and WDT
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FUNCTIONAL DESCRIPTION (Continued)
Mask Selectable Options. There are six Mask Selectable Options to choose from based on ROM code requirements. (See Table 7). Table 7. Mask Selectable Options Option Function TA = 0C, +55C Internal clock frequency equal to or less than 4.0 MHz Note: The internal clock frequency is one-half the external clock frequency. The Low Voltage trip voltage (VLV) is less than 2.1V under the following conditions: Maximum (VLV) Conditions:
Permanent Watch-Dog On/WDT command invoked Timer RAM Protect On/Off RC/Other RC/XTAL 32 kHz XTAL On/Off Port 04-07 Pull-ups On/Off Port 00-03 Pull-ups On/Off Port 31-33 Pull-ups On/Off Port 20-27 Pull-ups On/Off Port 3 Mouse Mode 0.4 VDD On/Off Trip Low Voltage Detection/Standby. An on-chip Voltage Comparator checks that the VCC is at the required level for correct operation of the device. Reset is globally driven when VCC falls below VLV (Vrf1). A small further drop in VCC causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. Typical Low-Voltage power consumption in this Low Voltage Standby mode (ILV) is about 45 A (varying with the number of Mask selectable options enabled). If the VCC is allowed to stay above VRAM, the RAM content is preserved. When the power level is returned to above VLV, the device will perform a POR and function normally (Figure 45). The minimum operating voltage varies with the temperature and operating frequency, while VLV varies with temperature only.
1.8 1.6 1.4 1.2
VLV
VLV
1 1.8 0.6 0.4 0.2 0 0 15 35 25 Temperature 45 55
Figure 44. Typical Z86L/CX2 Low Voltage vs Temperature at 8 MHz
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EXPANDED REGISTER FILE CONTROL REGISTERS (0D)
CTR0 (0D) 0H D7 D6 D5 D4 D3 D2 D1 D0 0 P34 as Port Output* 1 Timer8 Output 0 Disable T8 Time Out Interrupt 1 Enable T8 Time Out Interrupt 0 Disable T8 Data Capture Interrupt 1 Enable T8 Data Capture Interrupt 00 01 10 11 R R W W SCLK on T8 SCLK/2 on T8 SCLK/4 on T8 SCLK/8 on T8 0 No T8 Counter Time Out 1 T8 Counter Time Out Occured 0 No Effect 1 Reset Flag to 0
1
0 Modulo-N 1 Single Pass R R W W 0 1 0 1 T8 Disabled * T8 Enabled Stop T8 Enable T8
* Default Setting After Reset
Figure 45. TC8 Control Register ((0D) 0H: Read/Write Except Where Noted)
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CTR1 (0D) 1H D7 D6 D5 D4 D3 D2 D1 D0 Transmit Mode R/W 0 T16_OUT is 0 Initially 1 T16_OUT is 1 Initially Demodulation Mode R 0 No Falling Edge Detection R 1 Falling Edge Detection W W 0 No Effect 1 Reset Flag to 0
Transmit Mode R/W 0 T8_OUT is 0 Initially 1 T8_OUT is 1 Initially Demodulation Mode 0 No Rising Edge Detection R 1 Rising Edge Detection R 0 No Effect W 1 Reset Flag to 0 W Transmit Mode* 0 0 Normal Operation 0 1 Ping-Pong Mode 1 0 T16_OUT = 0 1 1 T16_OUT = 1 Demodulation Mode 0 0 No Filter 0 1 4 SCLK Cycle Filter 1 0 8 SCLK Cycle Filter 1 1 16 SCLK Cycle Filter Transmit Mode/T8/T16 Logic 0 0 AND 0 1 OR 1 0 NOR 1 1 NAND Demodulation Mode 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved Transmit Mode 0 P36 as Port Output * 1 P36 as T8/T16_OUT Demodulation Mode 0 P31 as Demodulator Input 1 P20 as Demodulator Input Transmit/Demodulation Modes 0 Transmit Mode* 1 Demodulation Mode
Note: Changing from one mode to another cannot be done without disabling the counter/timers.
*Default after Reset
Note: Care must be taken in differentiating Transmit Mode from Demodulation Mode. Depending on which of these two modes is operating, the CTR1 bit will have different functions.
Figure 46. T8 and T16 Common Control Functions ((0D) 1H: Read/Write) 6-62 PRELIMINARY DS97LVO0900
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Z86C72/C92/L72/L92 IR Microcontroller
CTR2 (0D) 02H D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 P35 is Port Output* P35 is TC16 Output Disable T16 Time-Out Interrupt Enable T16 Time-Out Interrupt
1
0 Disable T16 Data Capture Interrupt 1 Enable T16 Data Capture Interrupt 00 01 10 11 R R W W 0 1 0 1 SCLK on T16 SCLK/2 on T16 SCLK/4 on T16 SCLK/8 on T16 No T16 Time Out T16 Time Out Occurs No Effect Reset Flag to 0
Transmit Mode 0 Modulo-N for T16 1 Single Pass for T16 Demodulator Mode 0 T16 Recognizes Edge 1 T16 Does Not Recognize Edge R R W W 0 1 0 1 T16 Disabled * T16 Enabled Stop T16 Enable T16
* Default Setting After Reset
Figure 47. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)
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EXPANDED REGISTER FILE CONTROL REGISTERS (0D) (Continued)
SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON Reserved (Must be 0) Stop-Mode Recovery Source 000 POR Only * 001 Reserved 010 P31 0 11 P32 100 P33 101 P27 11 0 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON * Stop Recovery Level 0 Low * 1 High Stop Flag 0 POR * 1 Stop Recovery**
* Default Setting After Reset ** Default Setting After Reset and Stop-Mode Recovery
Figure 48. Stop-Mode Recovery Register ((0F) 0BH: D6-D0 = Write Only, D7=Read Only)
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SMR2 (0F) 0DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR only* 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level 0 Low* 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events will cause a Stop-Mode Recovery. *Default Setting After Reset
1
Figure 49. Stop-Mode Recovery Register 2 ((0F) DH: D2-D4, D6 Write Only)
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WDTMR (0F) 0F D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP 00 01 * 10 11
INT RC OSC External Clock 5 ms 256 TpC 10 ms 512 TpC 20 ms 1024 TpC 80 ms 4096 TpC
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0) * Default Setting After Reset
Figure 50. Watch-Dog Timer Mode Register ((0F) OFH: Write Only)
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Reserved (Must be 1) * Default Setting After Reset P37 comparator output only on E72 and L72
Figure 51. Port Configuration Register (PCON) ((0F) OH: Write Only)
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Z8(R) STANDARD CONTROL REGISTER DIAGRAMS
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open Drain* 1 Port 2 Push-pull 0 Digital Mode 1 Analog Mode 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 00 01 10 11 P33 = Input P34 = Output P33 = Input P34 = /DM P33 = /DAV1/RDY1 P34 = RDY1//DAV1
1
P27-P20 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT*
*Default Setting After Reset
Figure 54. Port 2 Mode Register (F6H: Write Only)
R249 IPR D7 D6 D5 D4 D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C>A>B 010 A>B>C 011 A>C>B 100 B>C>A 101 C>B>A 110 B>A>C 111 Reserved IRQ1,IRQ4,Priority (Group C) 0 IRQ1>IRQ4 1 IRQ4>IRQ1 IRQ0,IRQ2 Priority (Group B) 0 IRQ2>IRQ0 1 IRQ0>IRQ2
0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2
* Effects P34 and P35
Reserved (Must be 0)
Figure 52. Port 3 Mode Register (F7H: Write Only)
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
P00-P03 Mode 00 Output 01 Input* 1X A11-A8 Stack Selection 0 External 1 Internal* P17-P10 Mode 00 Byte Output 01 Reserved 10 AD7-AD0 11 High-Impedance AD7AD0, /AS, /DS, /R//W, A11-A8, A15-A12, If Selected External Memory Timing 0 Normal* 1 Extended P07-P04 Mode 00 Output 01 Input* 1X A15-A12 * Default Setting After Reset. Note: Only P00 and P07 are Available on Z86L71.
IRQ3,IRQ5Priority (Group A) 0 IRQ5>IRQ3 1 IRQ3>IRQ5 Reserved (Must be 0)
Figure 55. Interrupt Priority Register ((0) F9H: Write Only)
Figure 53. Port 0 and 1 Mode Register (F8H: Write Only)
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R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0
R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Bank Pointer Default Setting After Reset = 0000 0000 Working Register Pointer
IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = T16 IRQ4 = T8 Reserved (Must be 0) Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11 Default Setting After Reset = 0000 0000
Figure 59. Register Pointer ((0) FDH: Read/Write)
R254 SPH D7 D6 D5 D4 D3 D2 D1 D0
Figure 56. Interrupt Request Register ((0) FAH: Read/Write)
Stack Pointer Upper Byte (SP15-SP8)
R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
Figure 60. Stack Pointer High ((0) FEH: Read/Write)
1 Enables IRQ4-IRQ0 (D0 = IRQ0) Reserved (Must be 0) Reserved (Must be 0) 0 Master Interrupt Disable* 1 Master Interrupt Enable
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Lower Byte (SP7-SP0)
* Default Setting After Reset
Figure 57. Interrupt Mask Register ((0) FBH: Read/Write)
Figure 61. Stack Pointer Low ((0) FFH: Read/Write)
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Tag Sign Flag Zero Flag Carry Flag
Figure 58. Flag Register ((0) FCH: Read/Write)
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PACKAGE INFORMATION
1
Figure 62. 40-Pin DIP Package Diagram
Figure 63. 44-Pin PLCC Package Diagram
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Figure 64. 44-Pin QFP Package Diagram
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ORDERING INFORMATION
Z86L72/L92 8 MHz 40-pin DIP Z86L7208PSC 44-pin QFP Z86L7208FSC 16 MHz 40-pin DIP Z86C7216PSC 44-pin QFP Z86C7216FSC 44-pin PLCC Z86C7216VSC Z86C9216VSC 44-pin PLCC Z86L7208VSC Z86L9208VSC
1
Z86C72/C92
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
Codes
Package P = Plastic DIP F = Plastic Quad Flat Pack V = Plastic Chip Carrier Temperature S = 0C to +70C Speed 8 = 8 MHz 16 = 16 MHz Environmental C = Plastic Standard
Example:
Z 86L72 08 P S C is a Z86L72, 8 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. DS97LVO0900
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com 6-71
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